With a good understanding, you should be able to get away with 25 ns memories instead of 12 ns at these speeds. If you have questions about that, ask for help.ģ) Yes, you are starting to build a "pipeline" which allows one stage to work on the new address while another uses the previous.
#Altera quartus ii web edition msi how to
So the question isn't about the "fastest possible" solution but about how to get a whole circuit humming along at a reasonable 32MHz or so.Ĭonsider wire-wrap on protoboard instead of breadboard (with soldered power supply and decoupling, and good ground connections or even a ground plane) - easy enough prototyping and a whole lot more reliable - and "in period" so to speak.ġ) No additional time at all, if you are using them correctly (and counting in powers of two) - 163s are synchronous counters, not ripple counters like the 7493.Ģ) See the datasheet. If that's not possible, what would you change to make it work at such speeds?.If that is possible, how do I make chip 2 skip only the first clock cycle?.
That way while chip 1 reads a byte, chip 2 writes the previous one, effectively copying at 32MB/sec speed.
#Altera quartus ii web edition msi update
The maximum update delay of the 4 cascading counters i.e.I'm having trouble understanding the timings in the datasheets. I would control chip 2 writing with the CS pin. 01uF decoupling capacitors on the power rails and the SRAM's Vcc and GND pins), but I don't know if that's too fast for the chips.ĭuring the copy operation, pin CS and OE of chip 1 would be low, as well as pin WE of chip 2. I would like to use a 32 MHz clock (I know, that's a lot for a breadboard, but I hope to handle it by using uniform short wire lengths and some. The counters would be connected like this (I understand this is the fastest way to cascade them):
SA and DA would be stored inside synchronous 4bit binary counters (4 SN74F163AN chips each, datasheet), SB would reside in a buffer (SN74F541N), and I would use an identity comparator (2 SN74F521N) between SA and SB to eventually stop the counters, and thus the copy operation. The SRAM chips are 12ns 32Kx8 Renesas IDT71256SA ( datasheet). I would like to create a breadboard circuit that copies addresses "SA"."SB" of SRAM chip 1 to addresses "DA"+ of SRAM chip 2, as fast as possible. I don't really want to use an FPGA, I'm trying to do it the "old" way, like this guy did. I decided to begin with the video generation part, with a fast memory copier, independent of the main processor. I'm trying to build a retrocomputer, and learn digital electronics along the way.